1. Technical Field
The present invention relates to a semiconductor device, in particular to a small scale semiconductor device, typified by a Chip Scale Package (CSP), and to a method of fabricating a semiconductor device.
2. Related Art
Demands for reductions in size and reductions in thickness are increasing for integrated circuit packages in which semiconductor elements, such as semiconductor integrated circuits or the like, are packaged. Recently, focusing on semiconductor integrated circuit packages in fields where there are particular demands for reductions in thickness, Chip Scale Packages (CSP) have been proposed with spherical shaped terminals disposed in a lattice shape on the surface of semiconductor elements.
In Japanese Patent Application Laid-Open (JP-A) No. 2004-319638, a semiconductor device is described with an insulating layer disposed on a semiconductor substrate, a metal wiring layer disposed thereon, and post shaped electrodes formed to land portions of the metal wiring layer. In this semiconductor device, cavities of a cross shape are formed to the land portions, and the alignment precision of a mask for the post shaped electrode is raised by using these cavities as alignment marks.
Recently, higher precision is being demanded in the exposure alignment precision of each layer in semiconductor devices, in order to achieve even finer pitches and even finer patterning of semiconductor devices.